Simplified double magnetic tunnel junctions

ABSTRACT

A double magnetic tunnel junction includes a bottom reference layer having a first fixed magnetization and a first thickness and formed from at least one material. A first tunnel barrier is on the bottom reference layer. A free layer is on the first tunnel barrier and has a changeable magnetization. A second tunnel barrier is on the free layer. A multilayered top reference layer is formed on the second tunnel barrier having a second fixed magnetization that is opposite to the first fixed magnetization and a second thickness that is smaller than the first thickness, and equal to or greater than the third thickness.

BACKGROUND Technical Field

The present invention relates to magnetic tunnel junction devices and,more particularly, to magnetic random access memory cells using doublemagnetic tunnel junctions.

Description of the Related Art

Magnetoresistive random access memory (MRAM) cells may be formed usingmagnetic tunnel junction structures. In such a device, a “fixed”magnetic layer is separated from a “free” magnetic layer by a thininsulating barrier. When a voltage is applied across the device,electrons tunnel through the insulating barrier by quantum effects,creating a current. The orientation of the magnetization of the freelayer relative to the fixed layer determines how likely an electron isto tunnel across the barrier, such that the magnetization of the freelayer determines an effective resistance of the device that can bemeasured.

The magnetization of the free layer may be set using, e.g.,spin-transfer torque. By applying a spin-polarized current to the freemagnetic layer, angular momentum is transferred to the free layer andthe orientation of its magnetization can be changed. In this manner, abit of information may be stored in the MRAM cell and subsequently readout by applying a current and determining the resistance.

However, in conventional magnetic tunnel junction devices, where asingle tunnel barrier is used, the switching current used to set a stateof the device can be quite high. This problem may be addressed by usingdouble magnetic tunnel junction devices, where the free layer issandwiched between two insulating layers, with fixed layers above andbelow. In such a device, the spin current from each side of the freelayer may add, thereby lowering the switching current needed.

While such a structure effectively lowers the switching current, thethickness of the stack is nearly doubled relative to a single magnetictunnel junction device. Thick device stacks take longer to grow and etchduring fabrication, thereby increasing the cost and decreasing theefficiency of fabrication.

SUMMARY

A double magnetic tunnel junction includes a bottom reference layerhaving a first fixed magnetization and a first thickness and formed fromat least one material. A first tunnel barrier is on the bottom referencelayer. A free layer is on the first tunnel barrier and has a changeablemagnetization. A second tunnel barrier is on the free layer. Amultilayered top reference layer is formed on the second tunnel barrierhaving a second fixed magnetization that is opposite to the first fixedmagnetization and a second thickness that is smaller than the firstthickness, and equal to or greater than the third thickness.

A memory device includes a plurality of magnetoresistive random accessmemory (MRAM) cells. Each MRAM cell includes a bottom reference layerhaving a fixed magnetization and a first thickness between about 21 andabout 120 Angstroms, and is formed from at least one material to form asynthetic anti-ferromagnetic structure. A first tunnel barrier is on thebottom reference layer including an insulating material that is between5 and 20 Angstroms thick. A free layer is on the first tunnel barrierand has a changeable magnetization and is between 10 and 30 Angstromsthick. A second tunnel barrier is on the free layer. A top referencelayer has a fixed magnetization and a second thickness that issignificantly smaller than the first thickness. The top reference layerhas a fixed magnetization and a second thickness of about 20 Angstromsthat is smaller than the first thickness and also includes a firstmagnetic layer on the second tunnel barrier, a spacer on the firstmagnetic layer, a second magnetic layer including tungsten on thespacer, and an oxide cap on the second magnetic layer having a thicknessbetween 2 and 20 Angstroms. A plurality of control transistors, eachconnected to a respective MRAM cell, is configured to control reading ofinformation from and writing of information to the respective MRAM cell.

A method of forming a double magnetic tunnel junction includes forming abottom reference layer having a first fixed magnetization and a firstthickness, the bottom reference layer being formed from at least onematerial. A first tunnel barrier is formed on the bottom referencelayer. A free layer is formed on the first tunnel barrier and has achangeable magnetization and a third thickness. A second tunnel barrieris formed on the free layer. A top reference layer is formed on thesecond tunnel barrier and has a second fixed magnetization that isopposite to the first fixed magnetization and a second thickness that issmaller than the first thickness, and about the same as the thirdthickness.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 shows a double magnetic tunnel junction in accordance with thepresent principles;

FIG. 2 shows an ultra-thin top reference layer in accordance with thepresent principles;

FIG. 3 shows a method of forming a double magnetic tunnel junction inaccordance with the present principles; and

FIG. 4 shows an array of memory devices in accordance with the presentprinciples.

DETAILED DESCRIPTION

Embodiments of the present invention provide double magnetic tunneljunction devices that provide lowered switching current relative to asingle-barrier design and, furthermore, employ a thin top layer thatsignificantly reduces the overall thickness of the device.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, a diagram of a doublemagnetic tunnel junction device 100 is shown. The device 100 includes aninitial seed layer 102 formed on a bottom electrode 101. A bottomreference layer 104 is grown on the seed layer and may include one ormore constituent layers and may have a thickness of about 20 Å to about120 Å. The bottom reference layer 104 is formed to have a fixedmagnetization. It is specifically contemplated that the bottom referencelayer 104 may have a synthetic anti-ferromagnetic (SAF) structure thatis cobalt-platinum or cobalt-iridium based with ruthenium or iridiumspacers.

The bottom reference layer 104 may be a single layer region that isconstructed of a metal or metal alloy that includes one or more metalsexhibiting high spin polarization. In alternative embodiments, exemplarymetals for the formation of the bottom reference layer 104 include iron,nickel, cobalt, chromium, boron, and manganese. Exemplary metal alloysmay include the metals exemplified by the above. In another embodiment,the reference layer may be a multilayer arrangement having (1) a highspin polarization region formed from of a metal and/or metal alloy usingthe metals mentioned above, and (2) a region constructed of a materialor materials that exhibit strong perpendicular magnetic anisotropy(strong PMA). Exemplary materials with strong PMA that may be usedinclude a metal such as cobalt, nickel, platinum, palladium, iridium, orruthenium, and may be arranged as alternating layers. The strong PMAregion may also include alloys that exhibit strong PMA, with exemplaryalloys including cobalt-iron-terbium, cobalt-iron-gadolinium,cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium,iron-platinum, and/or iron-palladium. The alloys may be arranged asalternating layers. In one embodiment, combinations of these materialsand regions may also be employed.

A first barrier layer 106 is formed on the bottom reference layer 104.The barrier is formed from an appropriate insulator material and isformed at such a thickness as to provide an appropriate tunnelingresistance. Exemplary materials for the first barrier layer 106 includemagnesium oxide, aluminum oxide, and titanium oxide, or materials ofhigher electrical tunnel conductance, such as semiconductors orlow-bandgap insulators. The thickness of the first barrier layer 106will depend on the material selected. The first barrier layer may havean exemplary thickness of about 5 Å to about 20 Å.

A free layer 108 is formed on the first barrier layer 106. The freelayer 108 is formed from a magnetic material with a magnetization thatcan be changed in orientation relative to the magnetization orientationof the bottom reference layer 104. Exemplary materials for the freelayer 108 include alloys and/or multilayers of cobalt, iron, alloys ofcobalt-iron, nickel, alloys of nickel-iron, and alloys ofcobalt-iron-boron. The free layer 108 may have an exemplary thickness ofabout 10 Å to about 30 Å.

A second barrier layer 110 is formed on the free layer 108. It isspecifically contemplated that the second barrier layer 110 may have thesame composition and thickness as the first barrier layer 106, butalternative embodiments may include a second barrier layer 110 that isformed from a different material and at a different thickness.

A top reference layer 112 is formed on the second barrier layer 110. Thetop reference layer 112 has a fixed magnetization that is orientedopposite to the magnetization of the bottom reference layer 104. It isspecifically contemplated that the top reference layer 112 will havemultiple constituent layers, as described below, and will have anexemplary thickness of about 20 Å to about 40 Å.

A cap layer 114 is formed on the top reference layer 112. The cap layer114 may be formed from one or more different kinds of oxides. Exemplaryoxide materials for the cap layer 114 include metal oxides such oxidesof aluminum, oxides of magnesium, oxides of magnesium and titanium,oxides of magnesium and tantalum, oxides of titanium, oxides oftantalum, oxides of tungsten, oxides of iridium, oxides of zirconium,and oxides of ruthenium, among others. In one embodiment, the cap layermay be formed magnesium oxide and may have thickness of about 2 Å toabout 20 Å. A top electrode 116 is formed over the cap layer 114. It iscontemplated that the total double magnetic tunnel junction device 100may have a thickness of about 100 Å to about 150 Å, as compared to aconventional single tunnel junction device which may have a thickness ofabout 140 Å.

Referring now to FIG. 2, a more detailed view of the top reference layer112 is shown. The top reference layer 112 includes a first magneticlayer 202, a spacer layer 204, and a second magnetic layer 206. Thefirst magnetic layer 202 may be formed from, e.g., cobalt, iron,cobalt-iron, cobalt-iron-boron, or multi-layers thereof. The secondmagnetic layer 206 may be formed from similar materials to the firstmagnetic layer 202 or may have a different set of materials. The spacerlayer 204 plays two roles in the top reference layer. First, itgenerates two more interfaces with interfacial perpendicular magneticanisotropy. This increases the PMA of the top reference layer as awhole. Secondly, being formed from a heavy element, the spacer layerincreases the damping constant of the top reference layer 112, whichmakes the top reference layer 112 more stable under spin torque duringswitching.

The spacer layer 204 may be formed from, e.g., a heavy element or alloyof heavy elements to increase damping of the magnetic layers to maketheir magnetization stable under the application of a spin torque. Inone specific embodiment, it is contemplated that the spacer layer may beformed from tungsten. Alternative materials for the spacer layer 204 mayinclude one or more of, e.g., tantalum, molybdenum, iridium, ruthenium,hafnium, platinum, and rhodium.

Optimized top reference layer 112 can be 400° C. stable and show verystrong magnetic perpendicular anisotropy. In one example, when atungsten spacer was used, the top reference layer shows a very highmagnetic anisotropy field H_(K) of greater than about 10 kOe after beingannealed at 400° C. for one hour. It is specifically contemplated thatthe thickness of the top reference layer 112 may be about 20 Å which, ina first embodiment having a cobalt-platinum based bottom SAF referencelayer 104, provides a device 100 having a thickness of about 140 Å and atunnel magnetoresistance (TMR) of about 98%. In a second embodiment,having a cobalt-iridium bottom reference layer 104, the total thicknessof the device may be about 100 Å with a TMR of about 110%.

It is to be understood that the present invention will be described interms of a given illustrative architecture having a wafer; however,other architectures, structures, substrate materials and processfeatures and steps may be varied within the scope of the presentinvention.

It will also be understood that when an element such as a layer, regionor substrate is referred to as being “on” or “over” another element, itcan be directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

A design for an integrated circuit chip may be created in a graphicalcomputer programming language, and stored in a computer storage medium(such as a disk, tape, physical hard drive, or virtual hard drive suchas in a storage access network). If the designer does not fabricatechips or the photolithographic masks used to fabricate chips, thedesigner may transmit the resulting design by physical means (e.g., byproviding a copy of the storage medium storing the design) orelectronically (e.g., through the Internet) to such entities, directlyor indirectly. The stored design is then converted into the appropriateformat (e.g., GDSII) for the fabrication of photolithographic masks,which typically include multiple copies of the chip design in questionthat are to be formed on a wafer. The photolithographic masks areutilized to define areas of the wafer (and/or the layers thereon) to beetched or otherwise processed.

Methods as described herein may be used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

Reference in the specification to “one embodiment” or “an embodiment” ofthe present principles, as well as other variations thereof, means thata particular feature, structure, characteristic, and so forth describedin connection with the embodiment is included in at least one embodimentof the present principles. Thus, the appearances of the phrase “in oneembodiment” or “in an embodiment”, as well any other variations,appearing in various places throughout the specification are notnecessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”,“and/or”, and “at least one of”, for example, in the cases of “A/B”, “Aand/or B” and “at least one of A and B”, is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of both options (A andB). As a further example, in the cases of “A, B, and/or C” and “at leastone of A, B, and C”, such phrasing is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of the third listedoption (C) only, or the selection of the first and the second listedoptions (A and B) only, or the selection of the first and third listedoptions (A and C) only, or the selection of the second and third listedoptions (B and C) only, or the selection of all three options (A and Band C). This may be extended, as readily apparent by one of ordinaryskill in this and related arts, for as many items listed.

Referring now to FIG. 3, a method of forming a double magnetic tunneljunction device 100 is shown. Block 302 forms seed layer 102 on thebottom electrode 101. The seed layer 102 may, for example, be formed ona semiconductor substrate or may, alternatively, be a semiconductorsubstrate itself. A semiconductor substrate may be a bulk-semiconductorsubstrate. In one example, a bulk-semiconductor substrate may be formedfrom a silicon-containing material. Illustrative examples ofsilicon-containing materials suitable for the bulk-semiconductorsubstrate include, but are not limited to, silicon, silicon germanium,silicon germanium carbide, silicon carbide, polysilicon, epitaxialsilicon, amorphous Si, and multi-layers thereof. Although silicon is thepredominantly used semiconductor material in wafer fabrication,alternative semiconductor materials can be employed, such as, but notlimited to, germanium, gallium arsenide, gallium nitride, cadmiumtelluride, and zinc sellenide. A semiconductor substrate mayalternatively be a semiconductor on insulator substrate.

Block 304 forms the bottom reference layer 304. This may include forminga multilayer that includes one or more fixed magnetic layers, separatedby spacers. The bottom reference layer may be deposited on the seedlayer 302 by any appropriate deposition process including, e.g.,chemical vapor deposition (CVD), physical vapor deposition (PVD), atomiclayer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVDis a deposition process in which a deposited species is formed as aresult of chemical reaction between gaseous reactants at greater thanroom temperature (e.g., from about 25° C. about 900° C.). The solidproduct of the reaction is deposited on the surface on which a film,coating, or layer of the solid product is to be formed. Variations ofCVD processes include, but are not limited to, Atmospheric Pressure CVD(APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (EPCVD), andMetal-Organic CVD (MOCVD) and combinations thereof may also be employed.In alternative embodiments that use PVD, a sputtering apparatus mayinclude direct-current diode systems, radio frequency sputtering,magnetron sputtering, or ionized metal plasma sputtering. In alternativeembodiments that use ALD, chemical precursors react with the surface ofa material one at a time to deposit a thin film on the surface. Inalternative embodiments that use GCIB deposition, a high-pressure gas isallowed to expand in a vacuum, subsequently condensing into clusters.The clusters can be ionized and directed onto a surface, providing ahighly anisotropic deposition.

Block 306 forms the first barrier layer 106. As noted above, the firstbarrier layer may be formed from an appropriate from an appropriateinsulator material, such as a metal oxide. Alternatively, the firstbarrier layer 106 may be formed by metal deposition followed by anoxidation process. Block 308 forms the free layer 308 on the firstbarrier layer from a material having a changeable magnetization. Block310 forms the second barrier layer 110 on the free layer 308.

Block 312 forms the top reference layer 112 on the second barrier layer110. Block 312 first forms the first magnetic layer 202, followed by thespacer layer 204, and then the second magnetic layer 206. Block 314forms cap layer 114 on the top reference layer 112 from, e.g., anappropriate metal oxide. Block 314 may form the cap layer by anyappropriate process including, e.g., CVD, PVD, ALD, or GCIB.Alternatively, block 314 may deposit a layer of metal and then oxidizethe same by, e.g., natural oxidation or radical oxidation.

After formation of the device 100, block 316 performs an anneal. Theanneal may be performed at a temperature between about 300° C. and about400° C. for about 5 minutes to about 90 minutes. Block 318 etches thedevice 100 out of the planar sheet of material that has been formedusing any appropriate etch. In an alternative embodiment, etching outthe devices 100 may be performed before the anneal of block 316. It isspecifically contemplated that an anisotropic etch, such as a reactiveion etch (RIE), may be used to isolate the device 100.

RIE is a form of plasma etching in which during etching the surface tobe etched is placed on a powered electrode. During RIE, the surface tobe etched takes on a potential that accelerates the etching speciesextracted from plasma toward the surface, in which the chemical etchingreaction is taking place in the direction normal to the surface. Otherexamples of anisotropic etching that can be used at this point includeion beam etching, plasma etching or laser ablation. Block 320 formselectrical contacts to the device 100. This may include forming topelectrode 116 and forming electrical vias and interconnects to the topelectrode 116 and the bottom electrode 101.

Referring now to FIG. 4, an array of MRAM devices is shown. Each doublemagnetic tunnel junction 402 is connected to a respective transistor 404that controls reading and writing. A word line 406 provides data towrite to the magnetic tunnel junctions 402, while a bit line 410 and abit line complement 408 read data from the magnetic tunnel junction 402.In this manner, a large array of memory devices can be implemented on asingle chip. An arbitrarily large number of MRAM devices 402 can beemployed, within the limits of the manufacturing processes and designspecifications.

Writing data to a magnetic tunnel junction 402 includes passing acurrent through a MTJ. This current causes the direction ofmagnetization to switch between a parallel or anti-parallel state, whichhas the effect of switching between low resistance and high resistance.Because this effect can be used to represent the 1s and 0s of digitalinformation, the magnetic tunnel junctions 402 can be used as anon-volatile memory. Passing the current in one direction through themagnetic tunnel junction 402 causes the magnetization of the free layer108 to be parallel with that of the bottom reference layer 104, whilepassing the current in the other direction through the magnetic tunneljunction 402 causes the magnetization of the free layer 108 to beantiparallel to that of the bottom reference layer 104. Reading the bitstored in a given magnetic tunnel junction 402 involves applying avoltage (lower than that used for writing information) to the magnetictunnel junction 402 to discover whether the magnetic tunnel junctionoffers high resistance to current (“1”) or low resistance (“0”).

The methods and structures that have been described may be employed inany electrical device. For example, the memory devices that aredisclosed herein may be present within electrical devices that employsemiconductors that are present within integrated circuit chips.Integrated circuit chips that include the disclosed interconnects may beintegrated with other chips, discrete circuit elements, and/or othersignal processing devices as part of either (a) an intermediate product,such as a motherboard, or (b) an end product. The end product can be anyproduct that includes integrated circuit chips, including computerproducts or devices having a display, a keyboard or other input device,and a central processor.

It should be further understood that MRAM devices according toembodiments of the present principles can be employed in any computingapparatus that utilizes random access memory (RAM). For example, suchcomputing apparatuses can utilize the MRAM devices in lieu of or inaddition to RAM. Such computing apparatuses can include personalcomputers, mainframes, laptops, smart phones, tablet computers and othercomputing devices.

Having described preferred embodiments of simplified double magnetictunnel junctions (which are intended to be illustrative and notlimiting), it is noted that modifications and variations can be made bypersons skilled in the art in light of the above teachings. It istherefore to be understood that changes may be made in the particularembodiments disclosed which are within the scope of the invention asoutlined by the appended claims. Having thus described aspects of theinvention, with the details and particularity required by the patentlaws, what is claimed and desired protected by Letters Patent is setforth in the appended claims.

1. A double magnetic tunnel junction, comprising: a bottom referencelayer having a first fixed magnetization and a first thickness, andformed from at least one material; a first tunnel barrier on the bottomreference layer; a free layer on the first tunnel barrier having achangeable magnetization and having a third thickness; a second tunnelbarrier on the free layer; and a multilayered top reference layer on thesecond tunnel barrier having a second fixed magnetization that isopposite to the first fixed magnetization and a second thickness that issmaller than the first thickness, and equal to or greater than the thirdthickness.
 2. The double magnetic tunnel junction of claim 1, whereinthe top reference layer comprises: a first magnetic layer on the secondtunnel barrier; a spacer on the first magnetic layer; and a secondmagnetic layer on the spacer.
 3. The double magnetic tunnel junction ofclaim 2, wherein the first magnetic layer and the second magnetic layercomprise one of cobalt, iron, cobalt-iron, cobalt-iron-boron.
 4. Thedouble magnetic tunnel junction of claim 2, wherein the spacer includesa material selected from the group consisting of molybdenum, iridium,hafnium, platinum, and rhodium.
 5. The double magnetic tunnel junctionof claim 2, wherein the top reference layer further comprises an oxidecap on the second magnetic layer.
 6. The double magnetic tunnel junctionof claim 1, wherein the second thickness is about 20 Å.
 7. The doublemagnetic tunnel junction of claim 1, wherein the bottom reference layercomprises: a superlattice formed from one of cobalt-platinum orcobalt-iridium; and a synthetic anti-ferromagnetic spacer formed fromone of ruthenium or iridium.
 8. The double magnetic tunnel junction ofclaim 1, further comprising: a first electrode formed under the bottomreference layer; and a second electrode formed on the top referencelayer.
 9. The double magnetic tunnel junction of claim 1, wherein thebottom reference layer includes a thickness of about 80 Å to about 120Å, and wherein the top multilayered reference layer includes a thicknessof about 20 Å.
 10. A memory device, comprising: a plurality ofmagnetoresistive random access memory (MRAM) cells, each comprising: abottom reference layer having a fixed magnetization and a firstthickness, and formed from at least one material to form a syntheticanti-ferromagnetic structure; a first tunnel barrier on the bottomreference layer including an insulating material; a free layer on thefirst tunnel barrier having a changeable magnetization and is; a secondtunnel barrier on the free layer; and a top reference layer having afixed magnetization and a second thickness of that is smaller than thefirst thickness, comprising: a first magnetic layer on the second tunnelbarrier including cobalt or iron or an alloy thereof; a spacer on thefirst magnetic layer including tungsten; a second magnetic layer on thespacer including cobalt or iron or an alloy thereof; and an oxide cap onthe second magnetic layer having a thickness between 2 and 20 Angstroms;and a plurality of control transistors, each connected to a respectiveMRAM cell, configured to control reading of information from and writingof information to the respective MRAM cell.
 11. The memory device ofclaim 10, wherein the first magnetic layer and the second magnetic layerof each top reference layer comprise one of cobalt, iron, cobalt-iron,cobalt-iron-boron.
 12. The memory device of claim 10, wherein the spacerof the top reference layer includes a material selected from the groupconsisting of molybdenum, iridium, hafnium, platinum, and rhodium. 13.The memory device of claim 10, wherein the second thickness of each MRAMcell is about 100 Å.
 14. The memory device of claim 10, wherein thebottom reference layer of each MRAM cell comprises: a superlatticeformed from one of cobalt-platinum and cobalt-iridium; and a rubidiumsynthetic anti-ferromagnetic spacer.
 15. The memory device of claim 10,wherein each MRAM cell further comprises: a first electrode formed underthe bottom reference layer; and a second electrode formed on the topreference layer, wherein the first and second electrode are connected tothe respective control transistor.
 16. A method of forming a doublemagnetic tunnel junction, comprising: forming a bottom reference layerhaving a first fixed magnetization and a first thickness, the bottomreference layer being formed from at least one material; forming a firsttunnel barrier on the bottom reference layer; forming a free layer onthe first tunnel barrier having a changeable magnetization and having athird thickness; forming a second tunnel barrier on the free layer; andforming a multilayered top reference layer on the second tunnel barrierhaving a second fixed magnetization that is opposite to the first fixedmagnetization and a second thickness that is smaller than the firstthickness, and about the same as the third thickness.
 17. The method ofclaim 16, wherein forming the multilayered top reference layercomprises: forming a first magnetic layer on the second tunnel barrier;forming a spacer on the first magnetic layer; and forming a secondmagnetic layer on the spacer.
 18. The method of claim 17, furthercomprising forming an oxide cap on the second magnetic layer.
 19. Themethod of claim 16, wherein the second thickness is about 20 Å.
 20. Themethod of claim 16, wherein forming the bottom reference layer comprisesforming the bottom reference layer on a bottom electrode.